#ifndef  __CC1100_RF_SETTING__
#define  __CC1100_RF_SETTING__


#include    "CC1100_hal_rf.h"

/* Chipcon */
/* Product = CC1100 */
/* Chip version = F   (VERSION = 0x03) */
/* Crystal accuracy = 10 ppm */
/* X-tal frequency = 26 MHz */
/* RF output power = 0 dBm */
/* RX filterbandwidth = 541.666667 kHz */
/* Phase = 0 */
/* Datarate = 249.938965 kBaud */
/* Modulation = (7) MSK */
/* Manchester enable = (0) Manchester disabled */
/* RF Frequency = 432.999817 MHz */
/* Channel spacing = 199.951172 kHz */
/* Channel number = 0 */
/* Optimization = Current */
/* Sync mode = (3) 30/32 sync word bits detected */
/* Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX */
/* CRC operation = (1) CRC calculation in TX and CRC check in RX enabled */
/* Forward Error Correction = (0) FEC disabled */
/* Length configuration = (1) Variable length packets, packet length configured by the first received byte after sync word. */
/* Packetlength = 255 */
/* Preamble count = (2)  4 bytes */
/* Append status = 1 */
/* Address check = (0) No address check */
/* FIFO autoflush = 0 */
/* Device address = 0 */
/* GDO0 signal selection = ( 6) Asserts when sync word has been sent / received, and de-asserts at the end of the packet */
/* GDO2 signal selection = (41) CHIP_RDY */
/***************************************************************
 *  SmartRF Studio(tm) Export
 *
 *  Radio register settings specifed with C-code
 *  compatible #define statements.
 *
 ***************************************************************/
/*
#define CC1100_SETTING_FSCTRL1    0x12
#define CC1100_SETTING_FSCTRL0    0x00
#define CC1100_SETTING_FREQ2      0x10
#define CC1100_SETTING_FREQ1      0xA7
#define CC1100_SETTING_FREQ0      0x62
#define CC1100_SETTING_MDMCFG4    0x2D
#define CC1100_SETTING_MDMCFG3    0x3B
#define CC1100_SETTING_MDMCFG2    0xF3
#define CC1100_SETTING_MDMCFG1    0x22
#define CC1100_SETTING_MDMCFG0    0xF8
#define CC1100_SETTING_CHANNR     0x00
#define CC1100_SETTING_DEVIATN    0x00
#define CC1100_SETTING_FREND1     0xB6
#define CC1100_SETTING_FREND0     0x10
#define CC1100_SETTING_MCSM0      0x18
#define CC1100_SETTING_FOCCFG     0x1D
#define CC1100_SETTING_BSCFG      0x1C
#define CC1100_SETTING_AGCCTRL2   0xC7
#define CC1100_SETTING_AGCCTRL1   0x00
#define CC1100_SETTING_AGCCTRL0   0xB0
#define CC1100_SETTING_FSCAL3     0xEA
#define CC1100_SETTING_FSCAL2     0x2A
#define CC1100_SETTING_FSCAL1     0x00
#define CC1100_SETTING_FSCAL0     0x1F
#define CC1100_SETTING_FSTEST     0x59
#define CC1100_SETTING_TEST2      0x88
#define CC1100_SETTING_TEST1      0x31
#define CC1100_SETTING_TEST0      0x09
#define CC1100_SETTING_IOCFG2     0x29
#define CC1100_SETTING_IOCFG0D    0x06
#define CC1100_SETTING_PKTCTRL1   0x04
#define CC1100_SETTING_PKTCTRL0   0x05
#define CC1100_SETTING_ADDR       0x00
#define CC1100_SETTING_PKTLEN     0xFF
*/
const CC1100_HAL_RF_CONFIG CC1100_RfConfig = {
    0x12,   // FSCTRL1
    0x00,   // FSCTRL0
    0x10,   // FREQ2
    0xA7,   // FREQ1
    0x62,   // FREQ0
    0x2D,   // MDMCFG4
    0x3B,   // MDMCFG3
    0xF3,   // MDMCFG2
    0x22,   // MDMCFG1
    0xF8,   // MDMCFG0
    0x00,   // CHANNR
    0x00,   // DEVIATN
    0xB6,   // FREND1
    0x10,   // FREND0
    0x18,   // MCSM0
    0x1D,   // FOCCFG
    0x1C,   // BSCFG
    0xC7,   // AGCCTRL2
    0x00,   // AGCCTRL1
    0xB0,   // AGCCTRL0
    0xEA,   // FSCAL3
    0x2A,   // FSCAL2
    0x00,   // FSCAL1
    0x1F,   // FSCAL0
    0x59,   // FSTEST
    0x88,   // TEST2
    0x31,   // TEST1
    0x09,   // TEST0
    0x29,   // IOCFG2
    0x06,   // IOCFG0D
    0x04,   // PKTCTRL1
    0x05,   // PKTCTRL0
    0x00,   // ADDR
    0x36    // PKTLEN
};

#endif
